EMT Low Power SRAM Memories

The em-SRAM is a family of embedded SRAM memory macrocells and compilers providing ultra low leakage operation.

A wide range of word-sizes and memory sizes together with multiple column multiplexing options allow System on a Chip architects great flexibility in the use of embedded SRAM.

Different low power modes are available to control both the leakage and active currents in the SRAM memory. When used with EMT’s specialized BIST solutions, em-SRAM memories offer an unprecedented level of test coverage both in the memory and in the logic surrounding it.

Ultra Low Power

Leakage Current

• Optional usage of High Vt (HVT) implants in array and periphery
• Different power modes with decreasing leakage current usage

Active Current

Different techniques are used to reduce active power such as segmented word-line and others

Key Features

• 90 and 65nm Low Power CMOS process
• Memory Sizes: 2Kb to 1024Kb
• Memory Density: 1.6Mb/mm2 in 65nm
• Up to 80% cell efficiency in large memories
• Optional ECC: 6 parity bits for each 32 bits of data
• tKQ: 3ns with ECC (@128Kb)
• tKQ: 2ns without ECC (@128Kb)
• Row and Column Redundancy depending on macro size
• Flow Through and Pipelined modes
• Optional Byte Write
• Memory compiler increment: 2 or 4 rows, 4 columns
• Foundry proven memory cells
• Test multiplexing collar
• Complete test solution when used together with em-BIST test controllers