EMT Memory Compiler Technology

The increasing complexity and specialization of modern System on a Chip requires several types of memories: DRAM, SRAM, OTP, etc.

Fast design cycles require the use of memory compilers to allow chip architects fast and flexible exploration of the design space .

EMT new Memory Compiler technology is the first compiler engine capable of supporting all the different types of embedded memories.

Key Features

EMT memory compilers allow effeiceint generation of DRAM, SRAM, Flash, OTP amd other embedded memories.

Flexible aspect ratios through column and I/O multiplexing
Separate input and output buses
Flow Through, Pipelined Read options
Write-through mode
Duty-free clock cycle
Optional ECC
Advanced power reduction modes supported through sophisticated netlisting and layout tiling capabilities
Flexible redundancy support: 1 or 2 dimensions. Laser or e-fuses
Complete interface for EDA tools
Allows routing over the array with higher metal layers
Test multiplexing collar
Complete test solution when used together with em-BIST test controllers

EMT Memory Compilers

EMT set of memory compilers include:

em-SRAM:

• SPSRAM: Single-Port(1R1W) Synchronous SRAM
• SPSRAMRD: Single-Port(1R1W) Synchronous SRAM with Redundancy
• DPSRAM: Dual-Port(2R2W) Synchronous SRAM
• DPSRAMRD: Dual-Port(2R2W) Synchronous SRAM with Redundancy
• SRFRAM: Multi-Port(1R1W, 2W1R, 2R2W) Synchronous Register File

em-DRAM:

• 1TRAMRD: Single-Port(1RW) Synchronous 1T1C embedded DRAM with Redundancy

em-ROM:

• DROM: Synchronous Diffusion based ROM
• VROM: Synchronous Via based ROM
• OTPROM: One Time Programmable ROM

Compiler Outputs

EMT memory compilers can be run through a
Graphical User Interface (GUI), or in command
mode.

EMT memory compilers provide two main sets of
outputs, front-end and back-end.

Front-end information is the set of views required by designers in the architecture and logic design phases. Front-end models are generated once the architecture and logic design is confirmed.

It includes the following views:

• Synopsys .LIB
• Synopsys .STAMP
• Verilog Behavioral
• Antenna LEF
• Datasheet Document

Back-End information is the set of views required
to do the physical design of the target integrated
circuit. It includes the following views:

• GDS II Layout
• LEF View
• SPICE LVS Netlist
• Gate Level Verilog Netlist