EMT BIST Compiler Technology

em-BIST is a new Built In Self Test and Repair tool optimized for the nanometer generation.

It is built around at speed test of complex memory structures. Given the high number of memories embedded in a modern System on a Chip design, em-BIST support resource sharing at multiple levels, from memory controllers to fuse banks.

Key Features

• Full support for At-speed test
• IEEE P1500 interface
  • Controlled through JTAG or dedicated pins
• Integrated scan support
• Flexible repair schemes
  • Row only, Column only, Row and Column, Row and Block
• Single Fuse bank can be shared by multiple BIST controllers
• User definable patterns implemented in hardware or downloaded at run-time
• Comprehensive library of test patterns providing coverage for SRAM and DRAM faults
  • inter-port coupling faults for multiport memories
  • DRAM Refresh test
  • stuck open address decoder test
  • unique bit write/mask test
• Data slicing for wide memories
• Concurrent execution of patterns for memories of different types and sizes
• Diagnostic support for full bit-mapping
• Tests for ECC logic including
  • At-speed test
  • 100% stuck-at and transition fault coverage of ECC logic
  • ECC bypass mode
• Supports address and data scrambling
• Supports pipeline insertion to improve timing closure at the Place and Route stage while ensuring At-speed test
  

Memory Support

• Single Port SRAM
• Dual and Multiple Port SRAM
• ROM
• DRAM
• Flash
• OTP and MTP

Programmable Features

• User definable number of programmable instructions
• Supports from 1 to 8 operations per March element
  • 4 operations in inter-port test mode with concurrent reads and writes
  • user definable read and write data per operation
  • back-to-back reads and writes
• Flexible data backgrounds
  • user definable 4, 8, 12, or 16 bit register
  • including LFSR data generation
• Flexible address counters
  • up, down, fast row, fast column, fast row-Bank, and fast column- Bank